项目作者: chipsalliance

项目描述 :
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
高级语言: C++
项目地址: git://github.com/chipsalliance/verible.git
创建时间: 2019-11-07T00:04:47Z
项目社区:https://github.com/chipsalliance/verible

开源协议:Apache License 2.0

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