FPGA/ASIC Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor 返回
项目作者： BrianHGinc

项目描述 ：
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.
高级语言： Verilog
项目地址: git://github.com/BrianHGinc/Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor.git