DATC Robust Design Flow.
Please visit new repository: https://github.com/ieee-ceda-datc/RDF-2019
In recent years, there has been a slew of design automation contests and
released benchmarks. Past examples include ISPD place & route contests, DAC
placement contests, timing analysis contests at TAU, and CAD contests at ICCAD.
Additional contests are planned for upcoming conferences. These are interesting
and important events that stimulate the research of the target problems and
advance the cutting edge technologies. Nevertheless, most contests focus only
on the point tool problems and fail in addressing the design flow or
co-optimization among design tools. DATC RDF platform is
developed to direct attention to the overall design flow from logic design to
physical synthesis to manufacturability optimization. The goals are to provide:
DATC RDF consists of the following directory structure:
Flow configuration: ./000_configLogic synthesis: ./100_logic_synthesis./110_remove_dangling_netsFloorplanning: ./200_floorplanning./210_create_defPlacement: ./300_placementTiming measurement: ./310_write_def./320_timingGate sizing: ./400_gate_sizing./410_write_bookshelf./420_legalization./430_write_def./440_timingGlobal routing: ./500_gr_bench_gen./510_global_routeDetaile routing: ./600_dr_benchmark_checker./610_detail_routeBenchmarks ./benchmarksBinaries ./binUtility scripts ./utils
To give a first shot, please try runnning:
$ cd /path/to/your/workspace$ git clone <this_repository>$ cd datc_robust_design_flow$ ./run.sh my_suite
which runs logic synthesis, placement, gate sizing, and global router with
a simple test case.
The result of each stage can be found under the stage’s directory, e.g.,
./100_logic_synthesis/synthesis./200_floorplanning/bookshelf./300_placement/placement./400_gate_sizing/sizing./510_global_route/global_route./610_detail_route/detail_route
Every stage has the main run script (run_suite). The configuration of design flow
can be customized using the configuration script located at 000_config. We can
specify logic synthesis scenario, utilization of chip floorplan, placer, gate
sizer, as well as global router. You can find an example flow configuration at:
./000_config/config_simple.sh
DATC RDF has 26 benchmark circuits that are taken from
TAU Contest 2017.
Since TAU Contest 2017 did not release complete Liberty library, we remapped
the benchmark circuits into our own technology library.
The standard cell library of DATC RDF is based on the library of
ISPD’12/13 Gate Sizing Contest.
We took the LEF file from A2A methodology of UCSD (almost the same LEF file used
in ICCAD’15 TDP contest). Please refer to the paper for more details:
A. Kahng et al., “Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research,” GLSVLSI’14
Inside benchmarks/utils directory, theres’s a utility script named install_tau17_benchmarks.py.
Run it by:
$ python install_tau17_benchmarks.py
It will (1) download the benchmarks, (2) remap the benchmarks to the RDF cell library,
(3) remove the dangling wires, and (4) set up the benchmark directory.
Notes: The above python script only works with python of version greater than 3.
Also, it requires an additional module requests.
So, if you get an error ModuleNotFoundError: No module named ‘requests’,
please install it, for example, by:
$ sudo pip install requests
You can configure the DATC RDF Database with your preferred logic
synthesis scenarios, placers, timers, and global routers.
An example flow configuration is shown below:
#!/bin/bash# Benchmarksbench_suite=("cordic_ispd")# Logic Synthesissynth_scenarios=("st")max_fanout=16# Floorplanningutilization=0.5# Placementplacers=("EhPlacer")target_density=0.8# Timertimers=("iTimerC2.0")# Gate Sizingrun_gs=truesizers=("USizer2013")# Global Routingglobal_routers=("NCTUgr")tile_size=30num_layer=6adjustment=10safety=90# Detailed Routingdetail_routers=("NCTUdr")
The run_suite script sets up and runs the synthesis expriments. To launch a
batch job on the full set of TAU benchmarks, the script is invoked as:
run_suite all
The script lists available benchmarks in the bench_set array. Similarly,
possible synthesis “scenarios” are given in the scenario_set array. A user may
fill-out the provided script variables my_suite and my_scenarios to run a
customized experiment as: run_suite my_suite.
(The test_suite and test_scenario variables in the script illustrate the
customized setting.)
A scenario is currently defined by the ABC AIG optmization script,
int mapping command, and a Boolean indicating the use of timing
assertions (provided in the <benchmark>.timing file). The name aliases
for available ABC scripts and mapping commands are stored in the ./bin/abc.rc
file.
The resulting verilog netlist gets stores in
synthesis/<benchmark>.<scenario>/<benchmark>.v"
Bookshelf files are generated given the synthesis result. You can run this
stage with run_suite script, similar to logic synthesis stage, after
specifying the benchmarks and logic synthesis scenario in configuration file.
The results will be stored at the directory named:
bookshelf/<benchmark>.<scenario>
Currently, the following placer binaries are available:
After placement, you can see the placement plot. The plot file will be stored at:
placement/<benchmark>.<scenario>.<placer>
To measure the timing with ICCAD evaluation program, we need to generate
the def files of placement results. It will be done by run_suite script
inside the “310_write_def” directory.
After def file geneartion, you can measure the timing with the ICCAD evaluation
program at “320_timing” directory. Currently, iTimerC2.0 and UI-Timer are
available. All the files dumped by the ICCAD evaluation prgram will be stored at:
timing/<benchmark>.<scenario>.<placer>/out
You can generate the global routing benchmarks after placement, using therun_batch at 500_gr_bench_gen directory.
After the benchmark generation, you can now run global routing at510_globla_route. Currently, NCTUgr, FastRoute, and BFG-R are available
for global routing. After global routing, you can see the congestion map:
global_route/<benchmark>.<scenario>.<placer>.<router>/<benchmark>.Max_H.congestion.pngglobal_route/<benchmark>.<scenario>.<placer>.<router>/<benchmark>.Max_V.congestion.png
In RDF, global routing and detailed routing read input files based on ISPD 2008 Global Routing Contest and ISPD 2018 Initial Detailed Routing Contest, respectively.
Since there is no industrial standard format for connecting global routing and detailed routing, we develop a global routing guide translator to translate the output format of ISPD 2008 Global Routing Contest into the input format of routing guide used in ISPD 2018 Initial Detailed Routing Contest.
In ISPD 2018 Contest, a group of design rules and routing preference metrics are defined and stored in LEF/DEF files.
As in commercial routers, the output of a detailed router follows DEF format that can be read by any commercial layout tools.
Currently, NCTUdr is included, and more tools from winning teams will be included.
To turn on the gate sizing flow, you need to set the run_gs flag in your
flow configuration file. Note that the gate sizing takes very long time to run.
It can also be executed by run_suite scripts, inside the following directories:
./400_gate_sizing./410_write_bookshelf./420_legalization./430_write_def./440_timing