项目作者: germanbravolopez

项目描述 :
Master thesis - image filtering with FPGA
高级语言: VHDL
项目地址: git://github.com/germanbravolopez/image_filtering.git
创建时间: 2019-02-21T00:12:02Z
项目社区:https://github.com/germanbravolopez/image_filtering

开源协议:MIT License

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Master thesis - image filtering with Xilinx FPGA

The system designed presents an image capture method using a CMOS image sensor (OV7670 board) which connects to an FPGA through the
Pmod interface. It also has a subsystem that allows communication via VGA with a monitor for the projection of the results obtained from the different filters.

System architecture

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