Synthesizable RISC CPU (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Spartan6 FPGA.
nano-cpu32k
is a simple out-of-order superscalar RISC processor core.
Feature | nano-cpu32k |
---|---|
Superscalar | √ |
Out-of-order issue/execution | √ |
Boot Linux | √ |
L1 Cache & MMU | √ |
AXI4 Memory interface | √ |
Instruction fetch width | 4 (Configurable) |
Issue width | 2 (Configurable) |
Dynamic branch prediction | √ |
Synthesizable Verilog | √ |
FPGA Verified | √ |
Clock frequency on FPGA | >100MHz @Kintex-7 |
The micro-architecture overview is shown below.
python3
.make build
to generate the Verilog file build/ysyx_210479.v
Verilator
.make build_sim
to generate the simulation program build/emu
.build/emu --help
for a overview of supported options.Run the prebuilt Linux:
./build/emu --mode=standalone -b ./prebuilt/vmlinux.bin --flash-image=./prebuilt/bsp/program/flash/trampoline-flash.bin --reset-pc=0x30000000
Alternatively, using the --mode=difftest
option, you can do differential test between hardware implementation and C++ reference model.
run-test.sh
to test hardware design.A DDR3-based minimum SoC is provided on fpga\ddr3_alpha_soc
in the form of Vivado project.
fpga\ddr3_alpha_soc\PINs.xlsx
for hardware connections.prebuilt\bsp\program\loader\vmlinux-loader.bin
starting at address 0x0.