Fantasy console

Table of contents

• Hardware
  • CPU
    • Registers
    • Binary instruction format
  • Memory map
  • Devices
    • Interrupt controller
    • Cartridge controller
    • GPU
      • GPU commands reference
    • Input controller
    • RAM
• Software
  • Assembly

Hardware

CPU

Registers

• 16 bits wide
• R0 always reads 0, no effect on write
• R1..R15 - general purpose, RW
• PC - program counter, RO

Binary instruction format

Each instruction consists of 1 up to 5 bytes.

First byte is instruction description byte, rest is instruction operands

Description byte format is TT????? where TT is instruction type and rest of
bits are type-specific.

Instruction type may be of 11, 01, 10 and 00 where

• 00 is A-instruction
• 01 is M-instruction
• 10 is J-Instruction
• 11 is S-instruction

A-instruction uses three operands: A, B and C.
Value of register A is combined with B using operation specified by F and then
stored to register specified by C. A-instruction-specific bit format is as follows:
FFFxxI, where F specifies operation:

• 000 for addition
• 001 for substraction
• 010 for division
• 011 for multiplication
• 100 for bitwise xor
• 101 for bit shift
• 110 for bitwise and
• 111 for bitwise or
  Immediate indicates if B is an immediate value

M-instructions are using two operands and have this specific bit pattern:
FHWxAB. F is operation - 1 for store and 0 for load. High indicates if
0xFFFF should be added to memory address specified by operand in order to access
addresses above 0xFFFF. Word indicates if stored\loaded value is word or a
byte. First operand specifies memory address and second operand is either a
value to write in case of store or a destination register for load. AB bits
are set accordingly. Load can only have register as destination, so A is
unused if F is 0.

J-instruction are using two operands. First operand is a register to check for
condition and second operand is immediate or register containing address for a
jump. Specific bits: CCxxxI, where Condition may be one of

• 00 for greater than zero
• 01 for less than zero
• 10 for equal to zero
  I indicates that second operand is immediate.

S-instruction don’t have operands. Only first bit is significant, indicating if
it’s int for 1 or brk if it’s 0.

Memory map

Devices

Interrupt controller

Return address word:

• Stores PC when interrupt happened before jumping to handler

Interrupt mask byte:

• When bit is 1 - interrupt is masked
• When interrupt masked handler won’t be invoked when interrupt raised
• All interrupts are masked before interrupt handler is invoked
• 0 bit: Data transfer finished
• 1 bit: Cart presence changed
• 2 bit: GPU command finish
• 3 bit: GPU invalid command
• 4 bit: Input state change
• 5 bit: Clock
• 6 bit: Reserved
• 7 bit: Reserved

Interrupt flags byte:

• Indexes are same as in mask byte
• Bit set to 1 when interrupt is active
• Set corresponding bit to 0 to mark interrupt as handled

Interrupt handler address word

• Stores address to jmp to when interrupt is raised

Cartridge controller

Present byte:

• 1 when cartridge present
• 0 otherwise

SRC word:

• Starting address in cartridge mem to read from during data transfer

DST word:

• Starting address in main memory to write to during data transfer

LEN word:

• Length of buffer to transfer
• Non-zero when data transfer in progress
• Write non-zero value to start data transfer
• Resets to 0 when data transfer completed

GPU

Palette 48 bytes:

• Array of 16 colors
• Each color is 3 RGB bytes

Sprites 16384 bytes:

• Array of 512 sprites
• Sprite is 8x8 pixel grid
• Pixel is 4 bit index to pallete

Control byte:

• (IIII CCCC)
• (C) Command 4 bit index
  • Index of GPU command to execute
  • 0x0: blit
  • 0x1: line
  • 0x2: fill
  • 0x3: scroll
  • 0x4: pixel
  • Write command index to start executing command
  • Resets to 0 when command execution finished
• (I) Color 4 bits:
  • Index of color from palette to use when drawing

GPU commands reference

Input controller

Input state byte:

• (PCCCCCCC)
• (P) - button pressed state
• (C) - character of pressed button

RAM

Battery-backed: persists its contents without power
RAM: conventional RAM, 16bits width, byte-addressable

Software

Assembly

Syntax

<instruction>
.<command>

Commands:

• label - mark next instruction address as
• export - make available to use in another files
• import - use address from another file
• const - define constant value of named
• - ignore everything until eol, used as comment

Instructions

Instructions not implemented but can be improvised from existings ones: